View ADS1226IRGVRG4_699088.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Burr Brown Products from Texas Instruments
AD
S12
AD S12
25
26
ADS1225 ADS1226
SBAS346 - MAY 2006
24-Bit Analog-to-Digital Converter with One- and Two-Channel Differential Inputs and Internal Oscillator
FEATURES
* * * * * * * * * * * * * * * * * 100SPS Data Rate (High-Speed Mode) Single-Cycle Settling Easy Conversion Control with START Pin Automatic Shutdown Low Noise: 4VRMS Noise (High-Resolution Mode) Input Multiplexer with Two Differential Channels (ADS1226) Voltage Reference Supports Ratiometric Measurements Self-Calibrating Simple Read-Only 2-Wire Serial Interface Internal High-Impedance Input Buffer Internal Temperature Sensor Internal Oscillator Low-Power: 1mW While Operating, < 1A During Shutdown Analog and Digital Supplies: 2.7V to 5.5V
DESCRIPTION
The ADS1225 and ADS1226 are 24-bit delta-sigma analog-to-digital (A/D) converters. They offer excellent performance, ease-of-use, and low power in a small 4mm x 4mm QFN package and are well-suited for demanding high-resolution measurements, especially in portable and other space-saving and power-constrained applications. The ADS1225 and ADS1226 convert on command using a dedicated START pin. Simply pulse this pin to initiate a conversion. Data is read in a single cycle for retrieval over a 2-wire serial interface that easily connects to popular microcontrollers like the MSP430. After the conversion completes, the ADS1225 and ADS1226 automatically shuts down all circuitry. Internal features include a two-channel multiplexer (ADS1226), selectable input buffer, temperature sensor, and oscillator. The full-scale range is defined by the external voltage reference with support provided for up to a 5V differential input signal. Two operating modes allow for speed (100SPS data rate, 15VRMS noise) or resolution (4VRMS noise, 16SPS data rate). The ADS1225/6 supports 2.7 to 5.5V analog and digital supplies. Power consumption is 1mW while converting with 3V supplies. The ADS1225 and ADS1226 are fully specified over an extended industrial temperature range of -40C to +105C.
TEMPEN AVDD VREFP VREFN DVDD START AINP1 AINN1 AINP2 AINN2 Oscillator MODE MUX Buffer DS ADC Serial Interface SCLK DRDY/DOUT
APPLICATIONS
Hand-Held Instrumentation Portable Medical Equipment Industrial Process Control
MUX ADS1226 Only
BUFEN
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2006, Texas Instruments Incorporated
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted) (1)
ADS1225, ADS1226 AVDD to GND DVDD to GND Input current Analog input voltage to GND Digital input voltage to GND Maximum junction temperature Operating temperature range Storage temperature range (1) -0.3 to +6 -0.3 to +6 100, momentary 10, continuous -0.3 to AVDD +0.3 -0.3 to to AVDD +0.3 +150 -55 to +125 -50 to +150 UNIT V V mA mA V V C C C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
2
Submit Documentation Feedback
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
ELECTRICAL CHARACTERISTICS
All specifications at TA = -40C to +105C, AVDD = +5V, DVDD = +3V, and VREF = +5V, unless otherwise noted.
ADS1225, ADS1226 PARAMETER Analog Input Full-scale input voltage Absolute input voltage AINP - AINN Buffer off; AINP, AINN with respect to GND Buffer on; AINP, AINN with respect to GND Buffer off Buffer on Buffer off GND - 0.1 GND + 0.05 2 1 4 VREF AVDD + 0.1 AVDD - 1.5 V V V M G M TEST CONDITIONS MIN TYP MAX UNIT
Differential input impedance Common-mode input impedance System Performance Resolution Data rate Integral nonlinearity (INL) Offset error Offset error drift Gain error Gain error drift Common-mode rejection Analog power-supply rejection Digital power-supply rejection
24 High-Speed mode High-Resolution mode End-point fit 75 12 100 16 0.0005 60 0.3 0.004 0.3 At DC At DC, 10% in AVDD At DC, DVDD = 2.7V to 5.5V High-Speed mode 85 95 95 80 1.5 0.4 0.025 125 22 0.0020 200
Bits SPS (1) SPS (1) % of FSR (2) V V/C % ppm/C dB dB dB ppm of FSR, rms ppm of FSR, rms
Noise High-Resolution mode Temperature Sensor Temperature sensor voltage Temperature sensor coefficient Voltage Reference Input Reference input voltage Negative reference input Positive reference input Voltage reference impedance VREF = VREFP - VREFN 0.5 GND - 0.1 VREFN + 0.5 1.5 5 AVDD VREFP - 0.5 AVDD + 0.1 TA = +25C 106 360
mV V/C V V V M
(1) (2)
SPS = samples per second. FSR = full-scale range = 2 x VREF.
Submit Documentation Feedback
3
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = -40C to +105C, AVDD = +5V, DVDD = +3V, and VREF = +5V, unless otherwise noted.
ADS1225, ADS1226 PARAMETER Digital Input/Output VIH Logic levels VIL VOH VOL Input leakage Power Supply AVDD DVDD Shutdown AVDD = 5V, converting, buffer off AVDD current AVDD = 5V, converting, buffer on AVDD = 3V, converting, buffer off AVDD = 3V, converting, buffer on Shutdown DVDD current DVDD = 5V, converting DVDD = 3V, converting Total power dissipation Temperature Range Specified Operating Storage -40 -55 -60 +105 +125 +150 C C C AVDD = 5V, DVDD = 3V, buffer off AVDD = DVDD = 3V, buffer off 2.7 2.7 <1 285 405 265 385 <1 90 55 1.6 1 2.5 5.5 5.5 V V A A A A A A A A mW mW IOH = 1mA IOL = 1mA 0.8 DVDD GND - 0.1 0.8 DVDD 0.2 DVDD 10 DVDD + 0.1 0.2 DVDD V V V V A TEST CONDITIONS MIN TYP MAX UNIT
4
Submit Documentation Feedback
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
PIN CONFIGURATION
RGV PACKAGE QFN-16 4.0mm x 4.0mm (TOP VIEW)
16
15
14
13
VREFN
VREFP
DVDD
AVDD
START SCLK DRDY/DOUT BUFEN
1 2
12 11
GND AINN1 AINP1 NC
ADS1225
3 4 10 9
5
6
7 MODE
TEMPEN
GND
PIN DESCRIPTIONS - ADS1225
TERMINAL NAME START SCLK DRDY/DOUT BUFEN GND TEMPEN MODE NC NC AINP1 AINN1 GND VREFN VREFP AVDD DVDD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Analog Input Analog Input Ground Analog Input Analog Input Analog Digital ANALOG/DIGITAL INPUT/OUTPUT Digital Input Digital Input Digital Output Digital Input Ground Digital Input Digital Input Serial clock input Dual-purpose output: Data ready: indicates valid data by going low. Data output: outputs data, MSB first, on the rising edge of SCLK. Enables buffer after MUX Ground Selects temperature sensor input from MUX Selects between High-Speed and High-Resolution modes No connect No connect Analog channel 1 positive input Analog channel 1 negative input Analog and digital ground Negative reference input Positive reference input Analog power supply Digital power supply DESCRIPTION High: Start conversions; Low: Shutdown
NC
8
Submit Documentation Feedback
5
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
RGV PACKAGE QFN-16 4.0mm x 4.0mm (TOP VIEW)
16
15
14
START SCLK DRDY/DOUT BUFEN
1 2
13
VREFN
VREFP
DVDD
AVDD
12 11
GND AINN1 AINP1 AINN2
ADS1226
3 4 10 9
5
6
7 MODE
TEMPEN
PIN DESCRIPTIONS - ADS1226
TERMINAL NAME START SCLK DRDY/DOUT BUFEN MUX TEMPEN MODE AINP2 AINN2 AINP1 AINN1 GND VREFN VREFP AVDD DVDD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ANALOG/DIGITAL INPUT/OUTPUT Digital Input Digital Input Digital Output Digital Input Digital Input Digital Input Digital Input Analog Input Analog Input Analog Input Analog Input Ground Analog Input Analog Input Analog Digital Serial clock input Dual-purpose output: Data ready: indicates valid data by going low. Data output: outputs data, MSB first, on the rising edge of SCLK. Enables buffer after MUX Selects analog input from MUX Selects temperature sensor input from MUX Selects between High-Speed and High-Resolution modes Analog channel 2 positive input Analog channel 2 negative input Analog channel 1 positive input Analog channel 1 negative input Analog and digital ground Negative reference input Positive reference input Analog power supply Digital power supply DESCRIPTION High: Start conversions; Low: Shutdown
6
Submit Documentation Feedback
AINP2
MUX
8
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
TYPICAL CHARACTERISTICS
At TA = -40C to +85C, AVDD = +5V, DVDD = +3V, and VREF = +5V, unless otherwise noted.
ANALOG CURRENT vs TEMPERATURE
350 Buffer Off 325 AVDD = 5V 450 500 Buffer On AVDD = 5V
ANALOG CURRENT vs TEMPERATURE
Current (mA)
Current (mA)
300 275 AVDD = 3V 250
400 AVDD = 3V 350
225 200 -50 -25 0 25 50 75 100 125 Temperature (C) 300 -50 -25 0 25 50 75 100 125 Temperature (C)
Figure 1. DIGITAL CURRENT vs TEMPERATURE
120 AVDD = 5V 105 90 75 60 45 30 -55 -25 5 35 Temperature (C) 65 95 125 AVDD = 3V 400 450
Figure 2. ANALOG CURRENT vs SUPPLY VOLTAGE
Buffer On
Current (mA)
Current (mA)
350
300 Buffer Off 250
200 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVDD Supply Voltage (V)
Figure 3. DIGITAL CURRENT vs SUPPLY VOLTAGE
110
Figure 4. TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE
150
Temperature Sensor Voltage (mV)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
100 90
140 130 120 110 100 90 80 70 -55 -25 5 35 Temperature (C) 65 95 125
Current (mA)
80 70 60 50 40 DVDD Supply Voltage (V)
Figure 5.
Figure 6.
Submit Documentation Feedback
7
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
TYPICAL CHARACTERISTICS (continued)
At TA = -40C to +85C, AVDD = +5V, DVDD = +3V, and VREF = +5V, unless otherwise noted.
INTEGRAL NONLINEARITY vs INPUT VOLTAGE
15 -40C 10 -10C 5 0 -5 -10 -15 -5 -4 -3 -2 -1 0 1 2 3 4 5 Input Voltage, VIN (V) +25C Buffer Off 10 8 6
INTEGRAL NONLINEARITY vs INPUT VOLTAGE
-40C -10C +25C Buffer On
INL (ppm of FSR)
INL (ppm of FSR)
4 2 0 -2 -4 -6 -8 -10 -3.5 -2.5 -1.5 +55C +85C +105C
+105C +85C
+55C
-0.5
0.5
1.5
2.5
3.5
Input Voltage, VIN (V)
Figure 7. OFFSET vs TEMPERATURE
20 10 0.001 0 -10 -20 -30 -40 -50 -25 0 25 50 75 100 125 Temperature (C) -0.002 -50 -25 0 0.002
Figure 8. GAIN ERROR vs TEMPERATURE
Gain Error (%)
Offset (mV)
0
-0.001
25
50
75
100
125
Temperature (C)
Figure 9. NOISE vs INPUT VOLTAGE
3.5 3.0 High-Speed Mode Buffer Off 3.0 2.5 High-Speed Mode Buffer On
Figure 10. NOISE vs INPUT VOLTAGE
Noise (ppm of FSR, rms)
2.5 2.0 1.5 1.0 0.5 0 -5
Noise (ppm of FSR, rms)
-4 -3 -2 -1 0 1 2 3 4 5
2.0 1.5 1.0 0.5 0 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5
Input Voltage, VIN (V)
Input Voltage, VIN (V)
Figure 11.
Figure 12.
8
Submit Documentation Feedback
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
TYPICAL CHARACTERISTICS (continued)
At TA = -40C to +85C, AVDD = +5V, DVDD = +3V, and VREF = +5V, unless otherwise noted.
NOISE vs INPUT VOLTAGE
0.9 0.8 High-Resolution Mode Buffer Off 0.7 0.6 High-Resolution Mode Buffer On
NOISE vs INPUT VOLTAGE
Noise (ppm of FSR, rms)
Noise (ppm of FSR, rms)
-5 -4 -3 -2 -1 0 1 2 3 4 5
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Input Voltage, VIN (V)
0.5 0.4 0.3 0.2 0.1 0 -3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
Input Voltage, VIN (V)
Figure 13. NOISE HISTOGRAM
250 High-Speed Mode 80 High-Resolution Mode 70 200 60
Figure 14. NOISE HISTOGRAM
Occurrence
150
Occurrence -80 0 40 -40 80 120 -160 -120 160
50 40 30 20 10
100
50
0
0 -30 -25 -20 -15 -10 -5
0
5
10
15
20
25
30
Output Code
Output Code
Figure 15. HIGH-SPEED MODE DATA RATE vs TEMPERATURE
120 21
Figure 16. HIGH-RESOLUTION MODE DATA RATE vs TEMPERATURE
110
Data Period (SPS)
Data Period (SPS)
0 25 50 75 100 125
18
100
90
15
80
70 -50 -25 Temperature (C)
12 -50 -25 0 25 50 75 100 125 Temperature (C)
Figure 17.
Figure 18.
Submit Documentation Feedback
9
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
OVERVIEW
The ADS1225 and ADS1226 are 24-bit delta-sigma A/D converters. Figure 19 shows a conceptual diagram of the device. The ADS1225 has a single channel, while the ADS1226 allows for one of two input channels to be selected through a multiplexer. A buffer can also be selected to increase the input impedance. The modulator measures the differential input signal VIN = (AINP - AINN) against the differential reference VREF = (VREFP - VREFN). The full-scale input range is VREF. A 2-wire serial interface indicates conversion completion and provides the user with the output data. An internal oscillator allows for free-running of the ADS1225 and ADS1226. Two other pins are used to control the operation of the ADS1225 and ADS1226. The START pin initiates conversions. The MODE pin puts the device into one of two modes. In High-Speed mode, the device gives data at 100 samples per second (SPS). In High-Resolution mode, data comes out at 16SPS with lower noise. In both modes, the device has single-cycle settling, reducing the latency of the output data.
ANALOG INPUTS (AINx+, AINx-)
The input signal to be measured is applied to the input pins AINPx and AINNx. The positive internal input is generalized as AINP, and the negative internal input is generalized as AINN. The signal is selected though the input MUX, which is controlled by MUX, as shown in Table 1. The ADS1225 and ADS1226 accept differential input signals, but can also measure unipolar signals. When measuring unipolar (or single-ended) signals with respect to ground, connect the negative input (AINN) to ground and connect the input signal to the positive input (AINP). Note that when the ADS1225 and ADS1226 are configured this way, only half of the converter full-scale range is used since only positive digital output codes are produced. An input buffer can be selected to increase the input impedance of the A/D converter with the BUFEN pin. Table 1. Input Channel Selection with MUX
DIGITAL PIN MUX 0 1 SELECTED ANALOG INPUTS POSITIVE INPUT AINP1 AINP2 NEGATIVE INPUT AINN1 AINN2
TEMPEN
VREFP VREFN START VREF
S AINP1 AINN1 AINP2 AINN2 Oscillator MUX AINP AINN Buffer S VIN
DS ADC
Serial Interface
SCLK DRDY/DOUT
MODE
MUX ADS1226 Only
BUFEN
Figure 19. Conceptual Diagram of the ADS1225 and ADS1226
10
Submit Documentation Feedback
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
Analog Input Measurement Without the Input Buffer With the buffer disabled by setting the BUFEN pin low, the ADS1225 and ADS1226 measure the input signal using internal capacitors that are continuously charged and discharged. Figure 20 shows a simplified schematic of the ADS1225/6 input circuitry, with Figure 21 showing the on/off timings of the switches. The S1 switches close during the input sampling phase. With S1 closed, CA1 charges to AINP, CA2 charges to AINN, and CB charges to (AINP - AINN). For the discharge phase, S1 opens first and then S2 closes. CA1 and CA2 discharge to approximately VDD/2 and CB discharges to 0V. The constant charging of the input capacitors presents a load on the inputs that can be represented by effective impedances. Figure 22 shows the input circuitry with the capacitors and switches of Figure 20 by their effective impedances.
ESD Protection AVDD CA1 3pF AINPx MUX AINNx AINN S1 S2 CA2 3pF AVDD AVDD/2 AINP S1 S2 CB 6pF AVDD/2
AVDD/2 ZeffA = tSAMPLE/CA1 = 4MW AINPx ZeffB = tSAMPLE/CB = 2MW AINNx ZeffA = tSAMPLE/CA2 = 4MW AVDD/2
Figure 22. Effective Analog Input Impedances with the Buffer Off ESD silicon diodes protect the inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below GND by more than 100mV, and likewise do not exceed VDD by 100mV. This limitation is shown in Equation 1:
GND * 100mV t (AINP, AINN) t VDD ) 100mV
(1)
Analog Input Measurement with the Input Buffer When the buffer is enabled by setting the BUFEN pin high, a low-drift, chopper-stabilized input buffer is used to achieve very high input impedance. The buffer charges the input sampling capacitors, thus removing the load from the measurement. Because the input buffer is chopper-stabilized, the charging of parasitic capacitances causes the charge to be carried away, as if by resistance. The input impedance can be modeled by a single resistor, as shown in Figure 23.
Figure 20. Simplified Input Structure with the Buffer Turned Off
AINP 1GW tSAMPLE = 12ms ON S1 OFF ON S2 OFF AINN
Figure 23. Effective Analog Input Impedances with the Buffer On Note that the analog inputs (listed in the Electrical Characteristics table as Absolute Input Range) must remain between GND + 0.05V to AVDD - 1.5V. Exceeding this range degrades linearity and results in performance outside the specified limits.
Figure 21. S1 and S2 Switch Timing for Figure 20
Submit Documentation Feedback
11
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
TEMPERATURE SENSOR
Internal diodes provide temperature-sensing capability. By setting the TEMPEN pin high, the selected analog inputs are disconnected and the inputs to the A/D converter are connected to the anodes of two diodes scaled to 1x and 64x in current and size inside the MUX, as shown in Figure 24. By measuring the difference in voltage of these diodes, temperature changes can be inferred from a baseline temperature. Typically, the difference in diode voltages is 106mV at +25C, with a temperature coefficient of 360V/C. A similar structure is used in the MSC1210 for temperature measurement. For more information, see TI application report SBAA100, Using the MSC121x as a High-Precision Intelligent Temperature Sensor, available for download at www.ti.com.
TEMPEN AVDD
VOLTAGE REFERENCE INPUTS (VREFP, VREFN)
The voltage reference used by the modulator is generated from the voltage difference between VREFP and VREFN: VREF = VREFP - VREFN. The reference inputs use a structure similar to that of the analog inputs. A simplified diagram of the circuitry on the reference inputs is shown in Figure 25. The switches and capacitors can be modeled with an effective impedance of 250k.
VREFP VREFN
AVDD
AVDD ESD Protection
16pF
Zeff = 500kW
8I
1I AINP AINN
1X
8X
Figure 25. Simplified Reference Input Circuitry ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on the reference pins do not go below GND by more than 100mV, and likewise, do not exceed VDD by 100mV. This limitation is shown in Equation 2:
GND * 100mV t (VREFP, VREFN) t VDD ) 100mV (2)
AINP1 AINN1 AINP2 AINN2
MUX
Figure 24. Measurement of the Temperature Sensor in the Input
For best performance, bypass the voltage reference inputs with a 0.1F capacitor between VREFP and VREFN. Place the capacitor as close as possible to the pins. The differential voltage reference inputs and the wide range of operation (VREF can support up to AVDD) make ratiometric measurements easy to implement.
12
Submit Documentation Feedback
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
INTERNAL OSCILLATOR
The ADS1225 and ADS1226 have an internal oscillator and run without an external crystal or oscillator.
MODE
The ADS1225 and ADS1226 have two modes of operation, allowing for High-Speed or High-Resolution. By taking the MODE pin high, the data rate is approximately 100Hz with an rms noise of 15V. When the MODE pin is low, the ADS1225 and ADS1226 average multiple samples to increase the noise performance to 4V of rms noise with a data rate of 16Hz. Table 2 shows the MODE pin operation. Table 2. MODE Pin Operation for the ADS1225 and ADS1226
MODE PIN 0 1 MODE High-Resolution High-Speed DATA RATE 16SPS 100SPS NOISE 4Vrms 15Vrms
DATA READY/DATA OUTPUT (DRDY/DOUT)
This digital output pin serves two purposes. First, it indicates when new data is ready by going LOW. Afterwards, on the first rising edge of SCLK, the DRDY/DOUT pin changes function and begins to output the conversion data, most significant bit (MSB) first. Data is shifted out on each subsequent SCLK rising edge. After all 24 bits have been retrieved, the pin can be forced high with an additional SCLK. It then stays high until new data is ready. This configuration is useful when polling on the status of DRDY/DOUT to determine when to begin data retrieval.
START
The START pin provides easy and precise control of conversions. Pulse the START pin high to begin a conversion as shown in Figure 26 and Table 3. The completion of the conversion is indicated by the DRDY/DOUT pin going low. Once the conversion completes, the ADS1225 and ADS1226 automatically shut down to save power. They stay shut down until START is once again taken high to begin a new conversion.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising edge. As with CLK, this input may be driven with 5V logic regardless of the DVDD voltage. There is hysteresis built into this input, but care should still be taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise-and-fall times of SCLK are less than 50ns.
tSTART START
Conversion Data tCONV
DRDY/DOUT
SCLK ADS1225/6 Status
Converting
Shutdown
Figure 26. Controlling Conversion with the START Pin Table 3. START Pin Conversion Times for Figure 26
SYMBOL tSTART tCONV DESCRIPTION Minimum START pulse to initiate a conversion Conversion time High-Speed mode Conversion time High-Resolution mode MIN 17 8.0 45.5 13.3 83.3 MAX UNITS s ms ms
Submit Documentation Feedback
13
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
The ADS1225 and ADS1226 can be configured to continuously convert by holding the START pin high as shown in Figure 27. With START held high, a new conversion starts immediately after the previous conversion completes. This configuration continues until the START pin is taken low.
Table 4. Ideal Output Code vs Input Signal
Input Signal VIN (AINP - AINN) +VREF IDEAL OUTPUT CODE( (1)) 7FFFFFh 000001h 000000h FFFFFFh
)V REF 2 23 * 1
0
DATA FORMAT
The ADS1225 and ADS1226 output 24 bits of data in binary two's complement format. The least significant bit (LSB) has a weight of (VREF)/(223- 1). The positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 4 summarizes the ideal output codes for different input signals.
START Data Ready
*V REF 2 23 * 1
v *VREF
223 2 *1
23
800000h
(1)
Excludes effects of noise, INL, offset, and gain errors.
Data Ready
DRDY/DOUT
ADS1225/6 Status
Converting SCLK held low in this example.
Converting
Converting
Converting
Figure 27. Conversion with the START Pin Tied High
14
Submit Documentation Feedback
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
DATA RETRIEVAL
With the START pin high, the ADS1225 and ADS1226 continuously convert the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as illustrated in Figure 28 and Table 5. After this occurs, begin shifting out the data by applying SCLKs. Data is shifted out MSB first. It is not required to shift out all 24 bits of data, but the data must be retrieved before the new data is updated (see t2) or else it will be overwritten.
Data Data Ready MSB DRDY/DOUT 23 tPD tDS SCLK 1 tSCLK 22 21
Avoid data retrieval during the update period. DRDY/DOUT remain at the state of the last bit shifted out until it is taken high (see t6), indicating that new data is being updated. To avoid having DRDY/DOUT remain in the state of the last bit, shift a 25th SCLK to force DRDY/DOUT high (refer to Figure 29). This technique is useful when a host controlling the ADS1225 and ADS1226 is polling DRDY/DOUT to determine when data is ready.
New Data Ready LSB 0 tHD tUP 24 tSCLK tCONV
START Tied High
Figure 28. Data Retrieval Timing Table 5. Data Retrieval Times for Figure 28
SYMBOL tDS tSCLK tPD tHD tUP tCONV DESCRIPTION DRDY/DOUT low to first SCLK rising edge SCLK positive or negative pulse width SCLK rising edge to new data bit valid: propagation delay SCLK rising edge to old data bit valid: hold time Data updating: no readback allowed Conversion time (1/data rate), High-Speed mode Conversion time (1/data rate), High-Resolution mode
Data Data Ready New Data Ready
MIN 0 100
MAX
UNITS ns ns
50 0 29.5 8.0 45.5 49.2 13.3 83.3
ns ns s ms ms
DRDY/DOUT
23
22
21
0
SCLK
1
24
25
25th SCLK to Force DRDY/DOUT High
Figure 29. Data Retrieval with DRDY/DOUT Forced High Afterwards
Submit Documentation Feedback
15
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
SELF-CALIBRATION
Self-calibration can be initiated at any time, although in many applications the ADS1225 and ADS1226 drift performance is so good that the self-calibration performed automatically at power-up is all that is needed. To initiate self-calibration, apply at least two additional SCLKs after retrieving 24 bits of data. Figure 30 and Table 6 illustrate the timing pattern. The 25th SCLK will send DRDY/DOUT high. The falling edge of the 26th SCLK will begin the calibration cycle. Additional SCLK pulses may be sent after the 26th SCLK; however, activity on SCLK should be minimized during calibration for best results.
When the calibration is complete, DRDY/DOUT goes low, indicating that new data is ready. There is no need to alter the analog input signal applied to the ADS1225 and ADS1226 during calibration; the input pins are disconnected within the A/D converter and the appropriate signals are applied internally and automatically. The first conversion after a calibration is fully settled and valid for use. The time required for a calibration depends on two independent signals: the falling edge of SCLK and an internal clock derived from CLK. Variations in the internal calibration values change the time required for calibration (t8) within the range given by the min/max specs. t11 and t12 described in the next section are affected likewise.
Data Ready After Calibration
DRDY/DOUT
23
22
21
0 Calibration Begins
23
SCLK
1
24
25
26 tCAL
Figure 30. Self-Calibration Timing Table 6. Self-Calibration Time for Figure 30
SYMBOL tCAL DESCRIPTION First data ready after calibration MIN 187 MAX 313 UNITS ms
16
Submit Documentation Feedback
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
APPLICATION INFORMATION GENERAL RECOMMENDATIONS
The ADS1225 and ADS1226 are high-resolution A/D converters. Achieving optimal device performance requires careful attention to the support circuitry and printed circuit board (PCB) design. Figure 31 shows the basic connections for the ADS1225 and ADS1226. As with any precision circuit, be sure to use good supply bypassing capacitor techniques. A smaller value ceramic capacitor in parallel with a larger value tantalum capacitor works well. Place the capacitors, in particular the ceramic ones, close to the supply pins. Use a ground plane and tie the ADS1225 and ADS1226 GND pin and bypass capacitors directly to it. Avoid ringing on the digital inputs. Small resistors (100) in series with the digital pins can help by controlling the trace impedance. Place these resistors at the source end.
+5V 0.1mF +3V 0.1mF 16 15 14 13 10mF 0.1mF 10mF REF1004
Pay special attention to the reference and analog inputs. These inputs are critical to performance. Bypass the voltage reference using similar techniques to the supply voltages. The quality of the reference directly affects the overall accuracy of the device. Make sure to use a low noise and low drift reference such as the REF1004. Often, only a simple RC filter is needed on the inputs. The circuit limits the higher frequency noise. Avoid low-grade dielectrics for the capacitors and place them as close as possible to the input pins. Keep the traces to the input pins short, and carefully watch how they are routed on the PCB. After the power supplies and reference voltage have stabilized, issue a self-calibration command to minimize offset and gain errors.
VREFN
VREFP
AVDD
DVDD
100W 100W 100W 100W 100W
1 2 3 4
START SCLK ADS1226 DRDY/DOUT BUFEN
GND AINN1 AINP1 AINN2
12 220pF 11 10 9 0.1mF 220pF 301W 301W
TEMPEN
6
MODE
AINP2
MUX
5
7
8
Same as shown for AINP1 and AINN1.
100W 100W
Figure 31. Basic Connections
Submit Documentation Feedback
17
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
SMALL INPUT SIGNALS
Figure 32 shows the schematic of the ADS1225 for measuring small output signals such as the output of a bridge sensor or load cell. In this application, the load cell is combined with the ADS1225 and an MSP430 microcontroller. An OPA2333 is used to buffer the inputs and to provide the gain of the load cell signal. A 5V source is used as the reference and the excitation, although any clean source can create a proper ratiometric signal for the reference. A typical load cell with a bridge sensitivity of 2mV/V using a 5V source would have a full-scale output of 10mV. The recommended gain of the OPA2333, for this load cell using low-drift resistors, would be 1 + 2RF/RG = 100.8V/V. This value gives a full-scale
measurement of approximately 1V while keeping the noise contribution of the OPA2333 low. The noise is low enough compared to full-scale to create a several-thousand count weigh scale, even in High-Speed mode. For better accuracy, this noise could be lowered through either additional filtering or using the High-Resolution mode. It is important to make sure that the reference and inputs are clean from clocks or other periodic signals to prevent coupling. Isolate the analog from the digital supplies and grounds whenever possible.
+5V 10mF +5V Load Cell +5V 1/2 OPA2333 0.1mF VREFN 0.1mF AVDD VREFP
+3V 0.1mF DVDD START SCLK MSP430xxx or mC GND
DRDY/DOUT
RF 4.99kW RG 100W RF 4.99kW
ADS1225 1kW AINP1 1kW 0.22mF 0.1mF AINN1 MODE BUFEN TEMPEN GND
+3V
2RF G=1+ RG 1/2 OPA2333
0.1mF
Use low-drift resistors for RF and RG
Figure 32. Using the OPA2333 as a Gain Stage in Front of the ADS1225
18
Submit Documentation Feedback
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
LARGE INPUT SIGNALS
Many industrial applications require measurement of signals that go beyond 5V. The ADS1225 can be used to measure large input signals with the help of an INA159. The precision, level translation differential amplifier converts a 10V input to a 5V input scale. This design allows systems to be run from a single 5V supply without the need for higher voltage supplies for signal conditioning.
Figure 33 shows a basic schematic. The negative input of the INA159 is grounded while the positive input is allowed to swing from -10V to +10V. Similarly, the negative input of the ADS1225 is grounded while the positive input swings from 0.5V to +4.5V given the useful VOUT swing of the INA159. The larger signal is easily measured without the need for extra 10V supplies. See the INA159 data sheet for additional details.
+5V 10mF +5V 0.1mF AVDD VREFP DVDD START SCLK VREFN MSP430xxx or mC GND ADS1225 +3V MODE BUFEN AINN1 TEMPEN GND +3V 0.1mF
V+ -IN 100kW 20kW SENSE
0.1mF
DRDY/DOUT
OUT
1kW
AINP1 1 mF
VIN 10V
+IN
100kW
40kW
REF 2
40kW INA159 V-
REF 1
Figure 33. With the Help of an INA159, the ADS1225 Measures 10V Signals
Submit Documentation Feedback
19
ADS1225 ADS1226
www.ti.com
SBAS346 - MAY 2006
DRDY/DOUT
23 MSB
22
21
0 LSB 24
SCLK START Tied High
1
(a) Data Retrieval
DRDY/DOUT
23
22
21
0
SCLK START Tied High
1
24
25
(b) Data Retrieval with DRDY/DOUT Forced High Afterwards Data Ready After Calibration
DRDY/DOUT
23
22
21
0
Begin Calibration
SCLK START Tied High
1
24
25
26
(c) Self-Calibration
START
DRDY/DOUT
23
22
21
20
SCLK
1
(d) Single Conversions with START Pulse
Figure 34. Summary of Serial Interface Waveforms Table 7. Digital Pin Operations
INPUT DIGITAL PIN START BUFEN MUX (ADS1226 only) TEMPEN MODE PIN NO. 1 4 5 6 7 0 Shutdown Mode Buffer Off AINP1 - AINN1 Input Temperature Sensor Off High-Resolution Mode 1 Start Conversion Buffer On AINP2 - AINN2 Input Temperature Sensor On High-Speed Mode
20
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2006
PACKAGING INFORMATION
Orderable Device ADS1225IRGVR ADS1225IRGVRG4 ADS1225IRGVT ADS1225IRGVTG4 ADS1226IRGVR ADS1226IRGVRG4 ADS1226IRGVT ADS1226IRGVTG4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type QFN QFN QFN QFN QFN QFN QFN QFN
Package Drawing RGV RGV RGV RGV RGV RGV RGV RGV
Pins Package Eco Plan (2) Qty 16 16 16 16 16 16 16 16 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Low Power Wireless www.ti.com/lpw

▲Up To Search▲

Price & Availability of ADS1226IRGVRG4

	To Download ADS1226IRGVRG4 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .